Intel® Xeon Phi™ Coprocessor
Developer Training Event:
Salt Lake City, UT

Event Details:

Monday, September 8, 2014
Registration Begins: 8:30 AM
Presentation: 9:00 AM to 4:00 PM
Lunch will be provided.
 

University of Utah
Intermountain Network and Scientific Computation Center
INSCC Room 110
155 S 1452 East
Salt Lake City, UT 84112
 

Please complete a very brief pre-training questionnaire at the following URL:

http://www.colfax-intl.com/nd/svy.aspx?rslc

This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor. 

The session will cover: 

• An overview of parallel programming frameworks and optimization guidelines for multi-core CPUs (Intel® Xeon®) and many-core coprocessors (Intel® Xeon Phi™)
• Discussions about three layers of parallelism: SIMD, Threads, Cluster environment
• Tips for quick porting/development of HPC software applications
• Real-life examples of code and optimization techniques
• Hardware solution and corresponding software implementations, APIs, and framework

Register Now! 

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