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James Kowalski went to a planetarium on his 6th birthday. While in elementary school, he founded the Cranford Model Rocket Society. He was a member of Union County Amateur Astronomers, and a Civil Air Patrol Cadet. While in high school, he was awarded the Junior Engineering and Technical Society’s Medal of Excellence. He attended summer workshops in Astronomy at the Hayden Planetarium in New York and at the Newark Museum. At the University of Pennsylvania, Jim was a research assistant in the Astronomy Department and did calculations for the book “Stellar Interiors”, by Dr. Eva Novotny. Jim also worked as research assistant in physics and in electrical engineering. Jim worked summer jobs including the Engineering Department of the Elizabethtown Water company. After graduation, he worked as a computer design engineer at Digital Computer Controls, where he worked on microprogramming and hardware design including special multiply-and-divide hardware for minicomputers. Jim returned to Pennsylvania to work at Burroughs Corporation Large Scale Systems in Tredyffrin, working first on IO Module, and Memory Control Module, before joining the processor design group, where he microprogrammed the multiplication and division hardware, modeling the algorithms and simulating operation to generate optimal test operand sets. Jim also microprogrammed the B500 diagnostic minicomputer using a directly executed language. Following his time at Burroughs, Jim joined Cray Research at Cray Laboratories in Boulder, Colorado. The job was to design the follow on to the Cray-I Supercomputer. From Seymour Cray’s design, he learned the merits of simplicity. Burroughs had begun using a hardware description language on another project. At Cray Labs, bit level C programs were used for algorithm modeling and simulation. Due to company reprioritization, the Boulder Laboratory was reabsorbed into Minneapolis-based Cray Research, and Jim was hired by IBM in Poughkeepsie, to work on supercomputers for the Scientific and Engineering Processor Products Division in Kingston, NY. IBM was an engineer’s dream job, with highly developed infrastructure in terms of design methods, technology and human resource development. Jim worked on ASIC design for vector processor technology upgrades and for new processors, including the 3090 Vector Processor. Jim developed a design tool to model and chart junction temperatures on a ceramic multi-chip module. He was on task forces for processor architecture, interacting with Poughkeepsie, for multiprocessor evaluation, and for ad hoc proposal review. Jim was the SEPP liaison to the General Technology Division for semiconductors in Fishkill, NY, the Power Supply Group in Poughkeepsie and the multilayer ceramic board division in Endicott, NY. After six years at IBM, Jim’s former boss at Cray Laboratories asked him to visit San Diego and consider joining a startup BiCMOS semiconductor company, Silicon Connections Corporation (SCC). Working in startup environment gave Jim a chance to take on new roles such as memory chip verification and standard cell library manager. He used Synopsys Design Compiler for ASIC synthesis, and engaged in transistor level design and simulation for special computer arithmetic cells. The tiny company’s good technology and designers could not match the marketing of semiconductor giants in memories. Jim was offered a new position at Jet Propulsion Laboratory Ground Telecommunications (Deep Space Network), joining a colleague from SCC. Jim designed critical computer arithmetic hardware in Gallium Arsenide for the Block V Digital Receiver, carrier tracking loop ASIC and lead the design of three ASICS for the Suppressed Carrier. He simulated the JTAG IO testing for the Block V board, and generated test procedures to detect and diagnose production faults. He wrote a program to generate a netlist from algorithm description for the 64-chip MCD III board. Jim implemented the JTAG state machine in an early Xilinx FPGA. On loan to the Avionics Section, Jim did verilog designs for Shuttle Radar Topography Mission (SRTM) including the FPGA interfacing to GPS receiving controls from the Mongoose processor, and inertial measurement unit interface FPGA. Jim was lead FPGA designer on FPGAs for Primary Atomic Clock for Space including control logic, sensor and actuator interfaces, and IO bus design and for High Altitude Subsonic Parachute test electronics, including VHDL and c++ programming for a Star Microsystems processor and collecting data at multiple rates from GPS, temperature sensors, IMU, etc. In less than four months, algorithm, telemetry packaging and transfer to flash memory were implemented and tested. Jim wrote a program to upack the data and reconstruct the telemetry streams. Besides FPGA design, he worked in System Engineering roles for Metrology on SIM and AMD projects, writing the ICD’s. Jim worked in the power lab to develop verilog code for the Battery Control Board for Mars Exploratoy Rovers, (Spirit and Opportunity). He continued with the FPGA design from breadboard in Xilinx to Engineering Model in Rad-Hard Actel (now Mercury) technology. Jim programmed Actel FPGA’s in the MER clean room test. He devised a sequence of tests in LabView for Hardware verification. He followed the design through development in the BCB clean room and system integration in the Mars Laboratory clean room. After the successful deployment of MER rovers on Mars, Jim was asked to upgrade the functionality of the design and migrate it to a newer RTAX technology. He performed verilog verification, hardware implementation and test for the MSL mission (Curiosity). After 19 years at JPL, and 15 years in computer and semiconductor industry, Jim retired. Jim started his consulting firm, JKFPGA, and worked for Maryland-based Intelligent Designs, Inc. and Transformational Security, Inc. on digital signal processing applications, including SDR. After 5 years, Jim was approached to work for Bastion Technologies, Inc., as a Subject Matter Expert in Reliability Analysis. He supported the Mars2020 processor, doing reliability analysis on the RAD750 single board computer, an upgrade of the Mongoose used in SRTM.