WEBINAR: Improving Chip Reliability Through Synchronizer Optimization 

DESCRIPTION

In this webinar a panel of experts will discuss the role of synchronizer design in modern chip development.  Using traditional approaches, in both design and characterization of modern synchronizers, has resulted in reduced reliability.  However, tremendous advancements have been made to improve synchronizers through proper characterization by utilizing a newly available tool, MetaACE, that simulates synchronizer behavior.  By leveraging automated tools, the design and development of robust synchronizers is simple, fast and results in superior reliability.

WHO SHOULD ATTEND

Anyone involved with integrated circuit design, such as cell designers, SoC developers, verification engineers

AGENDA

1. Panel Introductions
2. Characterizing Synchronizers in Clock Domain Crossings and other surprising places
3. Synchronizer Reliability
4. Using Automated Simulation to Improve Synchronizer Reliability
5. Demo:  Automated Simulation of a publicly available synchronizer
6. Q & A

WHAT WILL YOU GAIN FROM THIS WEBINAR?

• The chief failure mechanism of synchronizers is metastability.  This webinar will show why characterizing metastability is more important than ever, especially with today’s nanoscale manufacturing processes.
• Learn why characterizing metastability is important and why what you are doing may fall short.
• See a demo of a new simulation tool (MetaACE) that will allow you to characterize your cells quickly, and easily.
• Get your own, free version of MetaACE and see how well your current synchronizers work.

PANEL OF EXPERTS

SALOMON (SHLOMI) BEER

Shlomi Beer received the B.Sc in computer engineering (Summa Cum Laude) and B.A in Physics (Summa Cum Laude) in 2004 and Ph.D. degree in computer engineering in 2014 from the Technion— Israel Institute of Technology, where he was a Haso-Plattner-institut (HPI) fellow.  His doctoral research broke new ground in metastability analysis and measurement and these results have been reported in nine scientific publications.

 During 2005 to 2011 he held engineering and algorithmic positions in Freescale Semiconductor. In 2014 he joined the Priceline group where he manages the data science and algorithmic division in the Israel research center. He authored several publications and patents in the field of computer architecture, VLSI systems, computer vision algorithms, bidding systems, statistical modeling and machine learning.  

JERRY COX

Jerry is is the Founder & CEO of Blendics and a Senior Professor in Computer Science and Engineering at Washington University. He received his BS, MS and ScD degrees in Electrical Engineering from MIT. From 1974 to 1991, he was chair of the Washington University CSE Department and in 1997 became founder and Vice President for Strategic Planning for Growth Networks. This venture-funded chip-set company sold to Cisco in 2000 and eventually led to the top-of-the-line Cisco router, the CRS-1. Over his professional career he has taught and done research in asynchronous computing and designed and built many digital systems, using both the synchronous and asynchronous approaches. He has published over 100 scientific papers and book chapters and has eight patents.

TOM CHANEY 

Tom is a Co-Founder and Senior Engineer at Blendics. His BS degree is from Kansas State University and his MS degree is from Washington University and both are in Electrical Engineering. He had a 38 year career (1965 to 2003) at Washington University as a research engineer. He was a leading team member in the Macromodular Computer Design project which developed a set of asynchronous computer building blocks. He was also the lead engineer for a high-speed ATM network switch (an ancestor of the Cisco CRS-1) that included a set of three full-custom ICs. During his career, he has spent more time testing the metastable performance of IC flip-flops than most people in the world. He has authored several historic papers on metastability and holds one patent related to metastability.

DAVID ZAR

Dave is a Co-Founder and Senior Engineering at Blendics.  He received his BS in Computer Science and his BS and MS in Electrical Engineering from Washington University. He spends his time between two startups, one of which is Blendics. At Blendics, he is involved with engineering issues related to asynchronous circuits as well as helping to define the company’s role in the EDA/Services field. In his former role as a Research Associate in Computer Science and Engineering at Washington University, he designed an ASIC standard-cell library for Mentor Graphics that is made freely available for education and research use.