PowerPro Platform Demo (Wednesday 3PM) 

Overview of Calypto's' SoC low power design platform

With the explosion of consumer electronics, designing for low power has become an important design constraint and a key differentiating factor. Come see how the patented Sequential Analysis Technology of PowerPro can enable you to achieve the lowest-power SoC design.

 This suite session demonstrates:

• RTL power optimization across an entire SoC, including automatic clock gating, memory gating            and light sleep controller generation

• Up to 60% power savings from our patented sequential analysis technology

• Upfront RTL power estimation using the built in logic synthesis engine

• Eliminate design risk with sequential formal verification using Calypto’s SLEC Pro product

• Automatic and manual use modes, allowing the engineer to use the best power reduction                   methods for each block

• PowerPro's robust ECO flow