Intel® Xeon Phi™ Coprocessor
Developer Training Event
San Diego, CA
Event Details:
Thursday, May 1, 2014
Registration Begins: 8:30AM
Presentation: 9:00AM to 4:00PM
Lunch will be provided.
University of California, San Diego
San Diego Supercomputer Center
10100 Hopkins Drive
La Jolla, CA 92093
Directions:
http://www.sdsc.edu/about/Visitorinfo.html
Arrival:
The Workshop will be held in the SDSC Auditorium, located on the ground floor (east side of the building, just off the driveway). Exit the parking structure to the East and SDSC sits on the north side of parking structure. Parking permits are required. Parking kiosks can be found on each floor near elevators.
Please complete a very brief pre-training questionnaire at the following URL:
http://www.colfax-intl.com/nd/svy.aspx?rsan
This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor.
The session will cover:
- An overview of parallel programming frameworks and optimization guidelines for multi-core CPUs (Intel® Xeon®) and many-core coprocessors (Intel® Xeon Phi™):
- Discussions about three layers of parallelism: SIMD, Threads, Cluster environment
- Tips for quick porting/development of HPC software applications
- Real-life examples of code and optimization techniques
- Hardware solution and corresponding software implementations, APIs, and framework