Wednesday, October 22, 2014
Registration Begins: 8:30AM
Presentation: 9:00AM to 4:00PM
Lunch will be provided.

University of California, Los Angeles
IDRE Visualization Portal
5628 Math Sciences Building
Los Angeles, CA 90095
https://idre.ucla.edu/directions

Please complete a very brief pre-training questionnaire at the following URL:
http://www.colfax-intl.com/nd/svy.aspx?rlax

This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor.

The session will cover:

• An overview of parallel programming frameworks and optimization guidelines for multi-core CPUs (Intel® Xeon®) and many-core coprocessors (Intel® Xeon Phi™)
• Discussions about three layers of parallelism: SIMD, Threads, Cluster environment
• Tips for quick porting/development of HPC software applications
• Real-life examples of code and optimization techniques
• Hardware solution and corresponding software implementations, APIs, and framework