Intel® Xeon Phi™ Coprocessor
Developer Training Event
Corvallis, OR

Event Details:

Tuesday, December 2, 2014
Registration Begins: 8:30 AM
Presentation: 9:00 AM to 4:00 PM
Lunch will be provided

Oregon State University
Kelley Engineering Center
Room 1007
Corvallis, OR 97331

Visitor parking instructions can be found at
http://parking.oregonstate.edu/visitor#Daily 

A daily permit for Zone A may be purchased for $12.00 at the Pay Station machine locations shown on the map link above. Click on the P symbols for permit information and parking maps. Pay stations accept credit cards and cash.

Please complete a very brief pre-training questionnaire at the following URL: 
http://www.colfax-intl.com/nd/svy.aspx?rcvo

This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor.

The session will cover:

• An overview of parallel programming frameworks and optimization guidelines for multi-core CPUs (Intel® Xeon®) and many-core coprocessors (Intel® Xeon Phi™)
• Discussions about three layers of parallelism: SIMD, Threads, Cluster environment
• Tips for quick porting/development of HPC software applications
• Real-life examples of code and optimization techniques
• Hardware solution and corresponding software implementations, APIs, and framework

Register Now! 

Privacy