Find Your City Below ...

Intel is offering an updated and expanded series of software developer trainings in parallel programming using the Intel^® Xeon^® and Xeon Phi^TM platforms.

This training seminar provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel^® Xeon^®and Intel^® Xeon Phi^TM platforms, including Intel’s next-generation Xeon Phi^TM processor, Knights Landing.

The course contains materials and practical exercises appropriate for developers beginning their journey to parallel programming, as well as provide cutting-edge detail to HPC experts on the best practices for Intel's multicore and many-core architectures and software development tools. This offering includes a one-day hybrid introductory lecture and hands-on laboratory (free).

The seminar features presentations on the available programming models and best optimization practices for the Intel Xeon and Intel Xeon Phi platforms, and on the usage of the Intel software development and diagnostic tools. The hands-on lab segment features hands-on exercises on the available programming models and best optimization practices for Intel Xeon and Xeon Phi platforms, and on the usage of the Intel development and diagnostic tools.  

Please note that the class will be capped at 40 students, and other students will be waitlisted (you will be notified via email if a slot opens up for you).

The training targets software engineers and architects, and covers the following topics:

• Intel^® Xeon Phi^TM architecture: purpose, organization, pre-requisites for good performance, future technology
• Programming models: native, offload, heterogeneous clustering
• Parallel frameworks: automatic vectorization, OpenMP, MPI
• Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics
• Knights Landing programming model: Introductory

Register for a workshop in your area by selecting from the list of cities and courses below.  Cities are being continuously added, so check back often.

US

California Santa Barbara Hybrid: January 21 Santa Barbara Hybrid WAIT LIST: January 21

Texas Houston Hybrid: March 1 Houston Hybrid WAIT LIST: March 1

 

Don't see a city near you? Click here to request a workshop!

*CDT 401 four-day workshops will be hosted in Sunnyvale, CA at the Colfax headquarters.  
Click here to register for a CDT 401 workshop.

 

Courses: Programming & Optimization with Intel Xeon and Xeon Phi Platforms
Colfax Developer Training (CDT) is an in-depth intensive course on efficient parallel programming of Intel Xeon and Xeon Phi product families. 

Hybrid Workshop CDT 101 + CDT 102: FREE Click here for seminar course abstract Click here  for lab course abstract

The 1-day hybrid workshop features presentations and hands-on exercises on the available programming models and best optimization practices for the Intel Xeon and Xeon Phi platforms, and on the usage of the Intel software development and diagnostic tools. NOTE:  This class will be capped at 40 students; other students will be waitlisted.  If a slot opens up, you will be notified.