Where
University of Chicago5730 South Ellis Ave
John Crerar Library
Kathleen A. Zar Room
Chicago, IL 60637
Driving Directions
Parallel Programming and Optimization with
Intel® Xeon Phi™ Coprocessors
Developer Training Event
Chicago, IL
Event Details: CDT 101
Thursday, May 21, 2015
Registration Begins: 8:30 AM
Presentation: 9:00 AM to 4:00 PM
Lunch will be provided
University of Chicago
John Crerar Library
Kathleen A. Zar Room
5730 S. Ellis Ave
Chicago, IL 60637
Parking: Visitors can use the 5525 South Ellis Avenue parking structure (C2 on this map)
Directions: The Kathleen A. Zar room is on the first floor of the John Crerar Library (B4 on the above map). Please tell the staff at the gate that you are attending the workshop in the Zar room.
Space is limited ... register early!
This one-day labs course features hands-on exercises on the available programming models and best optimization practices for the Intel Xeon Phi coprocessor and Intel Xeon processor, and on the usage of the Intel software development and diagnostic tools.
The session will cover:
- Intel Xeon Phi architecture: purpose, organization, pre-requisites for good performance, future technology
- Programming models: native, offload, heterogeneous clustering
- Parallel frameworks: automatic vectorization, OpenMP, MPI
- Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics