When

Wednesday October 21, 2015 from 8:30 AM to 4:00 PM EDT
Add to Calendar 

Where

Yale University 
17 Hillhouse Avenue
Room 101 - TEAL Classroom
New Haven, CT 06511  

 
Driving Directions 

Contact

Marissa Rogers
Plan 365 Inc. 
919-534-2239 
mrogers@plan365inc.com 
 

Parallel Programming and Optimization with
Intel® Xeon Phi™ Coprocessors
Developer Training Event
New Haven, CT

Event Details: CDT 101

Wednesday, October 21, 2015

Yale University
17 Hillhouse Avenue
Room 101 - TEAL Classroom
New Haven, CT 06511

See where it is located here
Parking - paid parking is available at Grove Street Garage 

Space is limited ... register early!

This one-day seminar features presentations on the available programming models and best optimization practices for the Intel Xeon Phi coprocessors, and on the usage of the Intel software development and diagnostic tools.  CDT 101 is a pre-requisite for the hands-on labs (CDT 102).

The session will cover:

  • Offload and Native:  "Hello World" to complex, using MPI>
  • Performance Analysis:  VTune.
  • Case Study:  All aspects of tuning in the N-body calculation.
  • Optimization I:  Strip-mining for vectorization, parallel reduction.
  • Optimization II:  Loop tiling, thread affinity.
Course abstract can be found here.

 

Reminder: You must complete CDT 101 before taking CDT 102