Thursday January 21, 2016 from 8:30 AM to 4:00 PM PST
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University of California -- Santa Barbara 
Elings Hall
Room 1601
Santa Barbara, CA 93106

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Marissa Rogers 
Plan 365 Inc. 

Parallel Programming and Optimization with
Intel® Xeon Phi™ Coprocessors
Developer Training Event
Santa Barbara, CA

Event Details: Hybrid Course

Thursday, January 21, 2016

University of California -- Santa Barbara
Elings Hall
Room 1601
Santa Barbara, CA 93106


Parking: Located at Lot 10, next to Elings Hall. There are two permit options: personal permit $10/day OR reserved space, $30 person
Permits may be purchased here
There is an express bus service available which runs at high frequency, and stops directly in front of Elings Hall. The schedule can be found here


This class is very popular.  If it is closed due to capacity,  please sign-up here.  If we get a cancellation, you will be moved into the class - first come, first served.  You will receive an email notification if you get moved to the class.

*Please bring your own laptop to the CDT 102 training, below is a list of the necessary specifications:

  • Windows (XP or newer), Mac OS X (10.5 or later), or Linux (something from the 21st century)
  • Wired (Ethernet) and wireless (Wi-Fi 802.11g or later) network connectivity
  • Web Browser (any)
  • On Windows: Putty and Pageant (www.putty.org) and WinSCP (www.winscp.net)
  • On Mac OS X and Linux: ssh client
  • Optional: on all operating systems, the free software NoMachine (www.nomachine.com). This is only necessary if you are not comfortable programming in Linux in a text terminal over an SSH connection. System requirements and installation instructions for NoMachine can be found here

This one-day training features presentations and hands-on exercises on the available programming models and best optimization practices for the Intel Xeon Phi coprocessors, and on the usage of the Intel software development and diagnostic tools. 

  • Offload and Native:  "Hello World" to complex, using MPI.
  • Case Study:  All aspects of tuning in the N-body calculation.
  • Optimization I:  Strip-mining for vectorization, parallel reduction.
  • Optimization II:  Loop tiling, thread affinity.
  • Intel Xeon Phi architecture: purpose, organization, prerequisites for good performance, future technology
  • Programming models: native, offload, heterogeneous clustering 
  • Parallel frameworks: automatic vectorization, OpenMP, MPI
  • Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics

Seminar abstract can be found here

Labs abstract can be found here