When

Tuesday, June 3, 2014 from 12:00 PM to 1:00 PM PDT
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Where

Moscone South - Booth 2333

747 Howard Street
San Francisco, CA 94103

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Contact

Mathilde Karsenti
Calypto Design Systems
503.970.7410
mkarsenti@calypto.com

Reaching for Maximum Power Reduction at RTL using PowerPro and SLEC (Tuesday 12:00 PM)

In this session, we describe how PowerPro’s accurate and fast RT Level power analysis combined with patented sequential optimization enables you to create optimal low power RTL designs that meet your power and design constraints and the automated sequential formal verification technology of SLEC Pro.

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