Friday, March 27, 2015
8:30 AM to 4:00 PM PDT

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Lawrence Berkeley National Laboratory 
Building 54, Room 130 (Perseverance Hall)
1 Cyclotron Road
Berkeley, CA 94720



Lisa Sonntag 
Plan 365 Inc. 

Parallel Programming and Optimization with
Intel® Xeon Phi™ Coprocessors
Developer Training Event
Berkeley, CA
Hosted by the LBNL IT Division High Performance Computing Services Group

Event Details:

Friday, March 27, 2015
Registration Begins: 8:30 AM
Presentation: 9:00 AM to 4:00 PM
Lunch will be provided

Lawrence Berkeley National Laboratory
Building 54, Room 130 (Perseverance Hall)
1 Cyclotron Road
Berkeley, CA 94720

Space is limited ... register early!

Travel instructions can be found here.
Attendees affiliated with DoE or UC do not need a shuttle pass. Just show your DoE/UC identification and let the driver know you are attending a workshop at Building 54 (Dining Hall).

This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors, which are available to Lab researchers and collaborators on the LBNL Lawrencium Cluster.

The session will cover:

  • Intel Xeon Phi architecture: purpose, organization, pre-requisites for good performance, future technology
  • Programming models: native, offload, heterogeneous clustering
  • Parallel frameworks: automatic vectorization, OpenMP, MPI
  • Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics
Course abstract can be found here.