Parallel Programming and Optimization with
Intel® Xeon Phi™ Coprocessors
Developer Training Event
Bloomington, IN

Event Details: CDT 101

Thursday, September 3, 2015

Indiana University
Cyberinfrastructure Building (CIB) - Multipurpose Room A
2709 E. 10th Street
Bloomington, IN 47408

Map of location

Parking & building information here

The map shows the E University Rd parking lot and the parking lot behind the Intercollegiate Athletics Gymnasium which are the best places to park. The CIB is clearly marked as is the entrances off of State Road 46 and 10th St.

Enter the complex from 10th St. at the Innovation Center drive or from State Road 46 at the Golf Course Drive (Range Road).  Valid IU parking permits are required.

Space is limited ... register early!

This one-day seminar features presentations on the available programming models and best optimization practices for the Intel Xeon Phi coprocessors, and on the usage of the Intel software development and diagnostic tools.  CDT 101 is a pre-requisite for the hands-on labs (CDT 102).

The session will cover:

• Offload and Native:  "Hello World" to complex, using MPI>
• Performance Analysis:  VTune.
• Case Study:  All aspects of tuning in the N-body calculation.
• Optimization I:  Strip-mining for vectorization, parallel reduction.
• Optimization II:  Loop tiling, thread affinity.

Course abstract can be found here.

 

Reminder: You must complete CDT 101 before taking CDT 102

Register Now! 

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