Implementing an Efficient RTL Clock Gating Analysis Flow at AMD

(Monday 3:00 PM) 

Presenter: Steve Kommrusch – Sr. Fellow Design Engineer, AMD

Description: Lowering the power consumption of consumer products and networking centers is an important design consideration. The same goes for many of the chips that go into these devices. AMD is building a reputation for designing power-efficient chips, which helps its end customers deliver lower-power products.

For the new low-power X86 AMD core code-named Jaguar, AMD wanted to improve on the previous generation in terms of faster performance in a given power envelope, higher frequency at a given voltage, and improved power efficiency through clock gating and unit redesign. The AMD low-power core design team used the Calypto® PowerPro® power analysis and optimization solution to analyze RTL clock-gating quality, get early power estimates, find opportunities for improvement, and generate reports usable by the engineering team to decrease the operating power of the design.

Because PowerPro analyzes pre-synthesis RTL, it can be run more often and analyze a larger number of simulation cycles more quickly and with fewer machine resources than tools that rely on synthesized gates for power analysis. The focus on clock gating and the quick turnaround of RTL analysis allowed AMD to achieve over 20% power reductions for typical applications of the AMD Jaguar core. 

In this private suite presentation, Steve Kommrusch from AMD will discuss AMD’s methodology for reducing power on the Jaguar SoC and will show how AMD used PowerPro to improve clock-gating efficiency. Steve will also share the results and advantages of doing power analysis and optimization at the RTL stage rather than waiting until post-gate synthesis.

Bio: Steve Kommrusch received his BS from University of Illinois in 1987 and his Masters  degree from Massachusetts Institute of Technology in 1989.  Steve has worked as a lead engineer on low power processors for over 15 years.  At Hewlett Packard, Steve worked on  a 3 ARM core ASIC for the CapShare 910 handheld scanner.  With National Semiconductor Steve worked on the Geode LX, an SOC with 2D graphics, X86 processor, and integrated display control which was in the OLPC laptop (One Laptop Per Child). Most recently Steve architected the clock, reset, and power control signals for the AMD Jaguar processor.   All of these products made extensive use of clock gating to improve battery life.